- Au_reefer wrote:
Be kind as I know fuckall about computers so speak slowly!!!
By the way, ok lets be kind.
Computers such as the ENIAC had to be physically rewired in order to perform different tasks, these machines are thus often referred to as "fixed-program computers." Since the term "CPU" is generally defined as a software (computer program) execution device, the earliest devices that could rightly be called CPUs came with the advent of the stored-program computer.
The idea of program computer was already present in the design of J. Presper Eckert and John William Mauchly's ENIAC, but was initially omitted so the machine could be finished sooner. On June 30, 1945, before ENIAC was even completed, mathematician John von Neumann distributed the paper entitled "First Draft of a Report on the EDVAC." It outlined the design of a stored-program computer that would eventually be completed in August 1949 [2]. EDVAC was designed to perform a certain number of instructions (or operations) of various types. These instructions could be combined to create useful programs for the EDVAC to run. Significantly, the programs written for EDVAC were stored in high-speed computer memory rather than specified by the physical wiring of the computer. This overcame a severe limitation of ENIAC, which was the considerable time and effort required to reconfigure the computer to perform a new task. With von Neumann's design, the program, or software, that EDVAC ran could be changed simply by changing the contents of the computer's memory.[3]
While von Neumann is most often credited with the design of the stored-program computer because of his design of EDVAC, others before him, such as Konrad Zuse, had suggested and implemented similar ideas. The so-called Harvard architecture of the Harvard Mark I, which was completed before EDVAC, also utilized a stored-program design using punched paper tape rather than electronic memory. The key difference between the von Neumann and Harvard architectures is that the latter separates the storage and treatment of CPU instructions and data, while the former uses the same memory space for both. Most modern CPUs are primarily von Neumann in design, but elements of the Harvard architecture are commonly seen as well.
As a digital device, a CPU is limited to a set of discrete states, and requires some kind of switching elements to differentiate between and change states. Prior to commercial development of the transistor, electrical relays and vacuum tubes (thermionic valves) were commonly used as switching elements. Although these had distinct speed advantages over earlier, purely mechanical designs, they were unreliable for various reasons. For example, building direct current sequential logic circuits out of relays requires additional hardware to cope with the problem of contact bounce. While vacuum tubes do not suffer from contact bounce, they must heat up before becoming fully operational, and they eventually cease to function due to slow contamination of their cathodes that occurs in the course of normal operation. If a tube's vacuum seal leaks, as sometimes happens, cathode contamination is accelerated. Usually, when a tube failed, the CPU would have to be diagnosed to locate the failed component so it could be replaced. Therefore, early electronic (vacuum tube based) computers were generally faster but less reliable than electromechanical (relay based) computers.
Tube computers like EDVAC tended to average eight hours between failures, whereas relay computers like the (slower, but earlier) Harvard Mark I failed very rarely [1]. In the end, tube based CPUs became dominant because the significant speed advantages afforded generally outweighed the reliability problems. Most of these early synchronous CPUs ran at low clock rates compared to modern microelectronic designs (see below for a discussion of clock rate). Clock signal frequencies ranging from 100 kHz to 4 MHz were very common at this time, limited largely by the speed of the switching devices they were built with.
Graphics accelerators
* A GPU (Graphics Processing Unit) is a processor attached to a graphics card dedicated to calculating floating point operations. A graphics accelerator incorporates custom microchips which contain special mathematical operations commonly used in graphics rendering. The efficiency of the microchips therefore determines the effectiveness of the graphics accelerator. They are mainly used for playing 3D games or high-end 3D rendering. A GPU implements a number of graphics primitive operations in a way that makes running them much faster than drawing directly to the screen with the host CPU. The most common operations for early 2D computer graphics include the BitBLT operation, combining several bitmap patterns using a RasterOp, usually in special hardware called a "blitter", and operations for drawing rectangles, triangles, circles, and arcs. Modern GPUs also have support for 3D computer graphics, and typically include digital video–related functions.
[edit] 1970s
The ANTIC and CTIA chips provided for hardware control of mixed graphics and text modes, sprite positioning and display (a form of hardware blitting), and other effects on Atari 8-bit computers. The ANTIC chip was a special purpose processor for mapping (in a programmable fashion) text and graphics data to the video output. The designer of the ANTIC chip, Jay Miner, subsequently designed the graphics chip for the Commodore Amiga.
[edit] 1980s
The IBM Professional Graphics Controller was one of the very first 2D/3D graphics accelerators available for the IBM PC. Released in 1984, 10 years before hardware 3D acceleration became a standard, its high price (~$4500 USD @ 1984 currency), slow processor (8088-2 running at 8MHz), and lack of compatibility with then-current commercial programs made it unable to succeed in the mass-market.
The Commodore Amiga was the first mass-market computer to include a blitter in its video hardware, and IBM's 8514 graphics system was one of the first PC video cards to implement 2D primitives in hardware.
The Amiga was unique, for the time, in that it featured what would now be recognized as a full graphics accelerator, offloading practically all video generation functions to hardware, including line drawing, area fill, block image transfer, and a graphics coprocessor with its own (primitive) instruction set. Prior to this (and quite some time after on most systems) a general purpose CPU had to handle every aspect of drawing the display.
[edit] 1990s
Tseng Labs ET4000/W32p
S3 Graphics ViRGE
Diamond Stealth 3 with S3 Savage 4 chip
In 1991, S3 Graphics introduced the first single-chip 2D accelerator, the S3 86C911, which its designers named after the Porsche 911 as an indication of the performance increase it promised. The 86C911 spawned a host of imitators: by 1995, all major PC graphics chip makers had added 2D acceleration support to their chips. By this time, fixed-function Windows accelerators had surpassed expensive general-purpose graphics coprocessors in Windows performance, and these coprocessors faded away from the PC market.
Throughout the 1990s, 2D GUI acceleration continued to evolve. As manufacturing capabilities improved, so did the level of integration of graphics chips. Additional application programming interfaces (APIs) arrived for a variety of tasks, such as Microsoft's WinG graphics library for Windows 3.x, and their later DirectDraw interface for hardware acceleration of 2D games within Windows 95 and later.
In the early and mid-1990s, CPU-assisted real-time 3D graphics were becoming increasingly common in computer and console games, which led to an increasing public demand for hardware-accelerated 3D graphics. Early examples of mass-marketed 3D graphics hardware can be found in fifth generation video game consoles such as PlayStation and Nintendo 64. In the PC world, notable failed first-tries for low-cost 3D graphics chips were the S3 ViRGE, ATI Rage, and Matrox Mystique. These chips were essentially previous-generation 2D accelerators with 3D features bolted on. Many were even pin-compatible with the earlier-generation chips for ease of implementation and minimal cost. Initially, performance 3D graphics were possible only with discrete boards dedicated to accelerating 3D functions (and lacking 2D GUI acceleration entirely) such as the 3dfx Voodoo. However, as manufacturing technology again progressed, video, 2D GUI acceleration, and 3D functionality were all integrated into one chip. Rendition's Verite chipsets were the first to do this well enough to be worthy of note.
OpenGL appeared in the early 90s as a professional graphics API, but became a dominant force on the PC, and a driving force for hardware development. Software implementations of OpenGL were common during this time although the influence of OpenGL eventually led to widespread hardware support. Over time a parity emerged between features offered in hardware and those offered in OpenGL. DirectX became popular among Windows game developers during the late 90s. Unlike OpenGL, Microsoft insisted on providing strict one-to-one support of hardware. The approach made DirectX less popular as a stand alone graphics API initially since many GPUs provided their own specific features, which existing OpenGL applications were already able to benefit from, leaving DirectX often one generation behind. (See: Comparison of OpenGL and Direct3D).
Over time Microsoft began to work more closely with hardware developers, and started to target the releases of DirectX with those of the supporting graphics hardware. Direct3D 5.0 was the first version of the burgeoning API to gain widespread adoption in the gaming market, and it competed directly with many more hardware specific, often proprietary graphics libraries, while OpenGL maintained a strong following. Direct3D 7.0 introduced support for hardware-accelerated transform and lighting (T&L). 3D accelerators moved beyond being just simple rasterizers to add another significant hardware stage to the 3D rendering pipeline. The NVIDIA GeForce 256 (also known as NV10) was the first card on the market with this capability. Hardware transform and lighting, both already existing features of OpenGL, came to hardware in the 90s and set the precedent for later pixel shader and vertex shader units which were far more flexible and programmable.
[edit] 2000 to present
With the advent of the OpenGL API and similar functionality in DirectX, GPUs added programmable shading to their capabilities. Each pixel could now be processed by a short program that could include additional image textures as inputs, and each geometric vertex could likewise be processed by a short program before it was projected onto the screen. NVIDIA was first to produce a chip capable of programmable shading, the GeForce 3 (code named NV20). By October 2002, with the introduction of the ATI Radeon 9700 (also known as R300), the world's first Direct3D 9.0 accelerator, pixel and vertex shaders could implement looping and lengthy floating point math, and in general were quickly becoming as flexible as CPUs, and orders of magnitude faster for image-array operations. Pixel shading is often used for things like bump mapping, which adds texture, to make an object look shiny, dull, rough, or even round or extruded. [2]
As the processing power of GPUs has increased, so has their demand for electrical power. High performance GPUs often consume more energy than current CPUs.[3] See also performance per watt and quiet PC.
Today, parallel GPUs have begun making computational inroads against the CPU, and a subfield of research, dubbed GPGPU for General Purpose Computing on GPU, has found its way into fields as diverse as oil exploration, scientific image processing, linear algebra[4], 3D reconstruction and even stock options pricing determination. There is increased pressure on GPU manufacturers from "GPGPU users" to improve hardware design, usually focusing on adding more flexibility to the programming model.[citation needed]
[edit] GPU companies
Many companies have produced GPUs under a number of brand names. In 2008, Intel, NVIDIA and AMD/ATI were the market share leaders, with 49.4%, 27.8% and 20.6% market share respectively. However, those numbers include Intel's very low-cost, less powerful integrated graphics solutions as GPUs. Not counting those numbers, NVIDIA and AMD control nearly 100% of the market. VIA Technologies, S3 Graphics and Matrox also produce GPUs.[5]
[edit] Computational functions
Modern GPUs use most of their transistors to perform calculations related to 3D computer graphics. They were initially used to accelerate the memory-intensive work of texture mapping and rendering polygons, later adding units to accelerate geometric calculations such as the rotation and translation of vertices into different coordinate systems. Recent developments in GPUs include support for programmable shaders which can manipulate vertices and textures with many of the same operations supported by CPUs, oversampling and interpolation techniques to reduce aliasing, and very high-precision color spaces. Because most of these computations involve matrix and vector operations, engineers and scientists have increasingly studied the use of GPUs for non-graphical calculations.
In addition to the 3D hardware, today's GPUs include basic 2D acceleration and framebuffer capabilities (usually with a VGA compatibility mode).
[edit] GPU accelerated video decoding
Most GPUs made since 1995 support the YUV color space and hardware overlays, important for digital video playback, and many GPUs made since 2000 also support MPEG primitives such as motion compensation and iDCT, this process of hardware accelerated video decoding, where portions of the video decoding process and video post-processing are offloaded to the GPU hardware, is commonly refered to as "GPU accelerated video decoding", "GPU assisted video decoding", "GPU hardware accelerated video decoding" or "GPU hardware assisted video decoding".
More recent graphics cards even decode high-definition video on the card, offloading the central processing unit. The most common API's for GPU accelerated video decoding are DxVA for Microsoft Windows operating-system, and VDPAU, VAAPI, XvMC, and XvBA for Linux and UNIX based operating-system. All except XvMC are capable of decoding videos encoded with MPEG-1, MPEG-2, MPEG-4 ASP (MPEG-4 Part 2), MPEG-4 AVC (H.264 / DivX 6), VC-1, WMV3/WMV9, Xvid / OpenDivX (DivX 4), and DivX 5 codecs, while XvMC is only capable of decoding MPEG-1 and MPEG-2.
[edit] Video decoding processes that can be accelerated
The video decoding processes that can be accelerated by todays modern GPU hardware are:
* Motion compensation (mocomp)
* Inverse discrete cosine transform (iDCT)
o Inverse telecine 3:2 and 2:2 pull-down correction
* Inverse modified discrete cosine transform (iMDCT)
* In-loop deblocking filter
* Intra-frame prediction
* Inverse quantization (IQ)
* Variable-Length Decoding (VLD), more commonly known as slice-level acceleration
* Spatial-temporal deinterlacing and automatic interlace/progressive source detection
* Bitstream processing (CAVLC/CABAC)
[edit] GPU forms
[edit] Dedicated graphics cards
Main article: Video card
The GPUs of the most powerful class typically interface with the motherboard by means of an expansion slot such as PCI Express (PCIe) or Accelerated Graphics Port (AGP) and can usually be replaced or upgraded with relative ease, assuming the motherboard is capable of supporting the upgrade. A few graphics cards still use Peripheral Component Interconnect (PCI) slots, but their bandwidth is so limited that they are generally used only when a PCIe or AGP slot is unavailable.
A dedicated GPU is not necessarily removable, nor does it necessarily interface with the motherboard in a standard fashion. The term "dedicated" refers to the fact that dedicated graphics cards have RAM that is dedicated to the card's use, not to the fact that most dedicated GPUs are removable. Dedicated GPUs for portable computers are most commonly interfaced through a non-standard and often proprietary slot due to size and weight constraints. Such ports may still be considered PCIe or AGP in terms of their logical host interface, even if they are not physically interchangeable with their counterparts.
Technologies such as SLI by NVIDIA and CrossFire by ATI allow multiple GPUs to be used to draw a single image, increasing the processing power available for graphics.
[edit] Integrated graphics solutions
Integrated graphics solutions, or shared graphics solutions are graphics processors that utilize a portion of a computer's system RAM rather than dedicated graphics memory. Computers with integrated graphics account for 90% of all PC shipments[6]. These solutions are less costly to implement than dedicated graphics solutions, but are less capable. Historically, integrated solutions were often considered unfit to play 3D games or run graphically intensive programs such as Adobe Flash[citation needed]. Examples of such IGPs would be offerings from SiS and VIA circa 2004.[7] However, today's integrated solutions such as AMD's Radeon HD 3200 (AMD 780G chipset) and NVIDIA's GeForce 8200 (NVIDIA nForce 730a) are more than capable of handling 2D graphics from Adobe Flash or low stress 3D graphics[8]. However, most integrated graphics still struggle with high-end video games. Chips like the Nvidia GeForce 9400M in Apple's MacBook and MacBook Pro and AMD's Radeon HD 3300 (AMD 790GX) have an improved performance, but still lag behind dedicated graphics cards. Modern desktop motherboards often include an integrated graphics solution and have expansion slots available to add a dedicated graphics card later.
As a GPU is extremely memory intensive, an integrated solution may find itself competing for the already relatively slow system RAM with the CPU, as it has minimal or no dedicated video memory. System RAM may be 2 Gbit/s to 12.8 Gbit/s, yet dedicated GPUs enjoy between 10 Gbit/s to over 100 Gbit/s of bandwidth depending on the model.
Older integrated graphics chipsets lacked hardware transform and lighting, but newer ones include it.[9]
Intel GMA X3000 IGP (under heatsink)
GMA X4500HD (Intel G45 chipset)
[edit] Hybrid solutions
This newer class of GPUs competes with integrated graphics in the low-end desktop and notebook markets. The most common implementations of this are ATI's HyperMemory and NVIDIA's TurboCache. Hybrid graphics cards are somewhat more expensive than integrated graphics, but much less expensive than dedicated graphics cards. These share memory with the system and have a small dedicated memory cache, to make up for the high latency of the system RAM. Technologies within PCI Express can make this possible. While these solutions are sometimes advertised as having as much as 768MB of RAM, this refers to how much can be shared with the system memory.
[edit] Stream Processing and General Purpose GPUs (GPGPU)
Main articles: GPGPU and Stream processing
A new concept is to use a general purpose graphics processing unit as a modified form of stream processor. This concept turns the massive floating-point computational power of a modern graphics accelerator's shader pipeline into general-purpose computing power, as opposed to being hard wired solely to do graphical operations. In certain applications requiring massive vector operations, this can yield several orders of magnitude higher performance than a conventional CPU. The two largest discrete (see "Dedicated graphics cards" above) GPU designers, ATI and NVIDIA, are beginning to pursue this new approach with an array of applications. Both nVidia and ATI have teamed with Stanford University to create a GPU-based client for the Folding@Home distributed computing project, for protein folding calculations. In certain circumstances the GPU calculates forty times faster than the conventional CPUs traditionally used by such applications.[10][11]
Recently NVidia began releasing cards supporting an API extension to the C programming language CUDA ("Compute Unified Device Architecture"), which allows specified functions from a normal C program to run on the GPU's stream processors. This makes C programs capable of taking advantage of a GPU's ability to operate on large matrices in parallel, while still making use of the CPU when appropriate. CUDA is also the first API to allow CPU-based applications to access directly the resources of a GPU for more general purpose computing without the limitations of using a graphics API.
Since 2005 there has been interest in using the performance offered by GPUs for evolutionary computation in general, and for accelerating the fitness evaluation in genetic programming in particular. There is a short introduction on pages 90–92 of A Field Guide To Genetic Programming. Most approaches compile linear or tree programs on the host PC and transfer the executable to the GPU to be run. Typically the performance advantage is only obtained by running the single active program simultaneously on many example problems in parallel, using the GPU's SIMD architecture[12][13]. However, substantial acceleration can also be obtained by not compiling the programs, and instead transferring them to the GPU, to be interpreted there[14][15]. Acceleration can then be obtained by either interpreting multiple programs simultaneously, simultaneously running multiple example problems, or combinations of both. A modern GPU (e.g. 8800 GTX or later) can readily simultaneously interpret hundreds of thousands of very small programs.
History and current usage
The front side bus is an alternative name for the data and address buses of the CPU as defined by the manufacturer's datasheet. The term is mostly associated with the various CPU buses used on PC-related motherboards (including servers etc), seldom with the data and address buses used in embedded systems and similar small computers.
Front side buses serve as a connection between the CPU and the rest of the hardware via a so-called chipset. This chipset is usually divided in a northbridge and a southbridge part, and is the connection point for all other buses in the system. Buses like the PCI, AGP, and memory buses all connect to the chipset in order for data to flow between the connected devices. These secondary system buses usually run at speeds derived from the front side bus clock, but are not necessarily synchronous to it.
In response to AMD's Torrenza initiative, Intel has opened its FSB CPU socket to third party devices [1]
[2]
. Prior to this announcement, made in Spring 2007 at Intel Developer Forum in Beijing, Intel had very closely guarded who had access to the FSB, only allowing Intel processors in the CPU socket. This is now changing, the first example being FPGA co-processors, a result of collaboration between Intel-Xilinx-Nallatech [3]
and Intel-Altera-XtremeData [4]
[5]
.
[edit] Related component speeds
[edit] CPU
The frequency at which a processor (CPU) operates is determined by applying a clock multiplier to the front side bus (FSB) speed in some cases. For example, a processor running at 3200 MHz might be using a 400 MHz FSB. This means there is an internal clock multiplier setting (also called bus/core ratio) of 8. That is, the CPU is set to run at 8 times the frequency of the front side bus: 400 MHz × 8 = 3200 MHz. By varying either the FSB or the multiplier, different CPU speeds can be achieved.
[edit] Memory
See also: Memory divider
Setting a FSB speed is related directly to the speed grade of memory a system must use. The memory bus connects the northbridge and RAM, just as the front side bus connects the CPU and northbridge. Often, these two buses must operate at the same frequency. Increasing the front-side bus to 450 MHz in most cases also means running the memory at 450 MHz.
In newer systems, it is possible to see memory ratios of "4:5" and the like. The memory will run 5/4 times as fast as the FSB in this situation, meaning a 400 MHz bus can run with the memory at 500 MHz. This is often referred to as an 'asynchronous' system. It is important to realize that due to differences in CPU and system architecture, overall system performance can vary in unexpected ways with different FSB-to-memory ratios.
In image, audio, video, gaming, FPGA synthesis and scientific applications that perform a small amount of work on each element of a large data set, FSB speed becomes a major performance issue. A slow FSB will cause the CPU to spend significant amounts of time waiting for data to arrive from system memory. However, if the computations involving each element are more complex, the processor will spend longer performing these; therefore, the FSB will be able to keep pace because the rate at which the memory is accessed is reduced.
[edit] Peripheral buses
Similar to the memory bus, the PCI and AGP buses can also be run asynchronously from the front side bus. In older systems, these buses are operated at a set fraction of the front side bus frequency. This fraction was set by the BIOS. In newer systems, the PCI, AGP, and PCI Express peripheral buses often receive their own clock signals, which eliminates their dependence on the front side bus for timing.
[edit] Overclocking
Main article: Overclocking
Overclocking is the practice of making computer components operate beyond their stock performance levels.
Many motherboards allow the user to manually set the clock multiplier and FSB settings by changing jumpers or BIOS settings. Almost all CPU manufacturers now "lock" a preset multiplier setting into the chip. It is possible to unlock some locked CPUs; for instance, some Athlons can be unlocked by connecting electrical contacts across points on the CPU's surface. For all processors, increasing the FSB speed can be done to boost processing speed by reducing latency between CPU and the northbridge.
This practice pushes components beyond their specifications and may cause erratic behavior, overheating or premature failure. Even if the computer appears to run normally, problems may appear under a heavy load. Most PCs purchased from retailers or manufacturers, such as Hewlett-Packard or Dell, do not allow the user to change the multiplier or FSB settings due to the probability of erratic behavior or failure. Motherboards purchased separately to build a custom machine are more likely to allow the user to edit the multiplier and FSB settings in the PC's BIOS.
[edit] Pros and cons
[edit] Pros
Although the front side bus architecture is an aging technology, it does have the advantage of high flexibility and low cost. There is no theoretical limit to the number of CPUs that can be placed on an FSB, though performance will not scale linearly across additional CPUs (due to the architecture's bandwidth bottleneck).
[edit] Cons
The front side bus as it is traditionally known may be disappearing, but it's still being used in all of Intel's Atom, Celeron, Pentium, and Core 2 processor models. Originally, this bus was a central connecting point for all system devices and the CPU. In recent years, this has been breaking down with the increasing use of individual point-to-point connections like AMD's HyperTransport and Intel's QuickPath Interconnect. The front side bus has been criticized by AMD as being an old and slow technology that bottlenecks today's computer systems. While a faster CPU can execute individual instructions faster, this is wasted if it cannot fetch instructions and data as fast as it can execute them; when this happens, the CPU must wait for one or more clock cycles until the memory returns its value. Furthermore, a fast CPU can be delayed when it must access other devices attached to the FSB. Thus, a slow FSB can become a bottleneck that slows down a fast CPU. FSB's fastest transfer speed is currently 1.6 GT/s, which provides only 80% of the theoretical bandwidth of a 16-bit HyperTransport 3.0 link as implemented on AM3 Phenom II CPUs, only half of the bandwidth of a 6.4 GT/s QuickPath Interconnect link, and only 25% of the bandwidth of a 32-bit HyperTransport 3.1 link. In addition, in an FSB-based architecture, the memory must be accessed via the FSB. In HT- and QPI-based systems, the memory is accessed independently by means of a memory controller on the CPU itself, freeing bandwidth on the HyperTransport or QPI link for other uses.
[edit] Transfer rates
This article may contain original research. Please improve it by verifying the claims made and adding references. Statements consisting only of original research may be removed. More details may be available on the talk page. (October 2009)
[edit] Intel processors
CPU FSB Clock Number of Cycles Bus Width Transfer Rate
Pentium 50 MHz-66 MHz 1 64-bit 400 MT/s-528 MT/s
Pentium Overdrive 25 MHz-66 MHz 1 64-bit 200 MT/s-528 MT/s
Pentium MMX 60 MHz-66 MHz 1 64-bit 480 MT/s-528 MT/s
Pentium MMX Overdrive 50 MHz-66 MHz 4 64-bit 400 MT/s-528 MT/s
Pentium II 66 MHz-100 MHz 1 64-bit 528 MT/s-800 MT/s
Pentium II Overdrive 60 MHz-66 MHz 4 64-bit 480 MT/s-528 MT/s
Pentium III 100 MHz-133 MHz 1 64-bit 800 MT/s-1064 MT/s
Pentium III-M 100 MHz-133 MHz 1 64-bit 800 MT/s-1064 MT/s
Pentium 4 100 MHz-133 MHz 4 64-bit 3200 MT/s-4256 MT/s
Pentium 4-M 100 MHz 4 64-bit 3200 MT/s
Pentium 4 HT 133 MHz-200 MHz 4 64-bit 4256 MT/s-6400 MT/s
Pentium 4 Extreme Edition 200 MHz-266 MHz 4 64-bit 6400 MT/s-8512 MT/s
Pentium D 133 MHz-200 MHz 4 64-bit 4256 MT/s-6400 MT/s
Pentium Extreme Edition 200 MHz-266 MHz 4 64-bit 6400 MT/s-8512 MT/s
Pentium M 100 MHz-133 MHz 4 64-bit 3200 MT/s-4256 MT/s
Core Solo 133 MHz-166 MHz 4 64-bit 4256 MT/s-5312 MT/s
Core Duo 133 MHz-166 MHz 4 64-bit 4256 MT/s-5312 MT/s
Core 2 Duo 133 MHz-333 MHz 4 64-bit 4256 MT/s-10656 MT/s
Core 2 Quad 266 MHz-333 MHz 4 64-bit 8512 MT/s-10656 MT/s
Core 2 Extreme 266 MHz-400 MHz 4 64-bit 8512 MT/s-12800 MT/s
Atom 133 MHz-166 MHz 4 64-bit 4256 MT/s-5312 MT/s
Celeron 66 MHz-266 MHz 1-4 64-bit 528 MT/s-8152 MT/s
Celeron D 133 MHz 4 64-bit 4256 MT/s
Celeron M 100 MHz-166 MHz 4 64-bit 3200 MT/s-5312 MT/s
Celeron Dual-Core 133 MHz-200 MHz 4 64-bit 4256 MT/s-6400 MT/s
Pentium Dual-Core 133 MHz-266 MHz 4 64-bit 4256 MT/s-8152 MT/s
Pentium II Xeon 200 MHz-266 MHz 1 64-bit 6400 MT/s-8152 MT/s
Pentium III Xeon 200 MHz-266 MHz 1 64-bit 6400 MT/s-8152 MT/s
Xeon 100 MHz-400 MHz 4 64-bit 3200 MT/s-12800 MT/s
Itanium 100 MHz-133 MHz 1 64-bit 800 MT/s-1064 MT/s
Itanium 2 100 MHz-166 MHz 4 64-bit 3200 MT/s-5312 MT/s
[edit] AMD processors
CPU FSB Clock Number of Cycles Bus Width Transfer Rate
Athlon 100 MHz-133 MHz 2 64-bit 1600 MT/s-2128 MT/s
Athlon XP 100 MHz-200 MHz 2 64-bit 1600 MT/s-3200 MT/s
Mobile Athlon 4 100 MHz 2 64-bit 1600 MT/s
Athlon XP-M 100 MHz-133 MHz 2 64-bit 1600 MT/s-2128 MT/s
Duron 100 MHz-133 MHz 2 64-bit 1600 MT/s-2128 MT/s
Sempron 166 MHz-200 MHz 2 64-bit 2656 MT/s-3200 MT/s
Athlon MP 100 MHz-133 MHz 2 64-bit 1600 MT/s-2128 MT/s
[edit] See also
There we go, thats us being kind on the info.
I love being a smartass lol.
Subject: help me upgrade 
Sun Jan 31, 2010 3:22 pm
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